Macnica's MEP100 SmartNIC Solution Is Now Shipping

Macnica is now shipping its MEP100 SmartNIC solution in advance of IBC 2024 (International Broadcasting Convention) this month, with the first units now operational within a major U.S-based global broadcaster’s on-premise media workflows.

Formally introduced at NAB Show in April, IBC marks the EMEA debut of the 100Gb hardware device, which drives ST 2110 media processing, stream protection and bandwidth utilization in a powerful, compact form factor. Macnica exhibits at Stand 14.D05.

Designed to meet the growing demand for IP solutions in the broadcast and ProAV industries, the MEP100 from Macnica was built to meet the needs of broadcasters establishing ST 2110 networks in their facilities. The MEP100 is interoperable with hardware and software products, offering developers a diverse creative platform for the broadcast and ProAV industries. The MEP100 also pairs naturally with Macnica’s M2S solution, which extends ST 2110 and IPMX workflows to streaming media networks and connects to all hardware points including common IT systems and computers. MEP100 customers will receive the M2S SDK at no additional cost.

New for IBC, Macnica has added JPEG-XS compression technology through its FPGA-based on-board architecture, making it possible to manage compressed ST 2110 streams alongside uncompressed streams. JPEG-XS compression delivers visually lossless quality, allowing customers to preserve bandwidth through compressed while maintaining sub-frame latency. Macnica will demonstrate the MEP100’s high-performance benefits in an on-booth exhibit of an end-to-end ST 2110 4K/HD networking ecosystem in its IBC stand in the RAI Amsterdam (September 13-16).

Macnica has equipped the MEP100 SmartNIC card with powerful resources to optimize performance and reliability of uncompressed media transport over ST 2110 IP networks. That begins with an FPGA hardware acceleration engine that offers product developers significant advantages over software-based alternatives. For example, ST 2110 IP packets are processed within the MEP100's FPGA IP core architecture, including processing of 2022-7 Seamless Protection Switching, freeing valuable CPU and memory bandwidth resources for the intended application.

Operationally, the MEP100’s full ST 2110 stack transfers video, audio and data directly to and from GPU memory or to application memory through kernel bypass technology. Paired with dedicated PTP acceleration, network path redundancy, on-board JPEG-XS compression and the M2S SDK, the MEP100 includes everything required for seamless ST 2110 integration with the customer’s application.

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